Method for improving the thermal stability of silicide

ABSTRACT

An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer  110 . The method may include forming an interface layer  200  over the semiconductor substrate  20  and performing an anneal to create a silicide  190  on the top surface of the gate electrode  110.

BACKGROUND OF THE INVENTION

This invention relates to the improvement of silicide structures locatedwithin the top portion of the polysilicon gates of semiconductortransistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor structure inaccordance with the present invention.

FIGS. 2A-2G are cross-sectional diagrams of a process for forming atransistor in accordance with the present invention.

FIG. 3 is a graphical comparison of the sheet resistance (as a functionof process temperature) of a standard silicide and a silicide formed inaccordance with the principles of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is described with reference to the attachedfigures, wherein like reference numerals are used throughout the figuresto designate similar or equivalent elements. The figures are not drawnto scale and they are provided merely to illustrate the invention.Several aspects of the invention are described below with reference toexample applications for illustration. It should be understood thatnumerous specific details, relationships, and methods are set forth toprovide a full understanding of the invention. One skilled in therelevant art, however, will readily recognize that the invention can bepracticed without one or more of the specific details or with othermethods. In other instances, well-known structures or operations are notshown in detail to avoid obscuring the invention. The present inventionis not limited by the illustrated ordering of acts or events, as someacts may occur in different orders and/or concurrently with other actsor events. Furthermore, not all illustrated acts or events are requiredto implement a methodology in accordance with the present invention.

Referring to the drawings, FIG. 1 is a cross-sectional view of asemiconductor structure 10 in accordance with the present invention. Inthe example application, CMOS transistors are formed within asemiconductor substrate 20 having an NMOS region 30 and a PMOS region40. However, it is within the scope of the invention to use asemiconductor structure 10 that contains any one of a variety ofsemiconductor devices, such as a bipolar junction transistor or a diode.

The CMOS transistors are electrically insulated from other activedevices (not shown) by shallow trench isolation structures 50 formedwithin the semiconductor substrate 30, 40; however, any conventionalisolation structure may be used such as field oxide regions (also knownas “LOCOS” regions) or implanted isolation regions. The semiconductorsubstrate 20 is a single-crystalline substrate that is doped to ben-type and p-type; however, it may be formed by fabricating an epitaxialsilicon layer on a single-crystal substrate.

Transistors are generally comprised of a gate, source, and drain. Morespecifically, as shown in FIG. 1, the active portion of the transistorsare comprised of source/drain regions 80, source/drain extension regions90, and a gate that is comprised of a gate oxide 100 and gate electrode110.

The example PMOS transistor 120 is a p-channel MOS transistor. Thereforeit is formed within a n-well region 40 of the semiconductor substrate20. In addition, the source and drain regions 80 (as well as the mediumdoped source and drain extension regions 90) have p-type dopants. ThePMOS gate is created from p-type doped polysilicon 110 and a gate oxidedielectric 100.

Similarly, the example NMOS transistor 130 is a n-channel MOStransistor. Therefore it is formed within a p-well region 30 of thesemiconductor substrate 20. In addition, the source and drain regions 80(as well as the medium doped source and drain extension regions 90) haven-type dopants. The NMOS gate is created from n-type doped polysilicon110 and a gate oxide dielectric 100.

A sidewall structure comprising offset layers 140, 150 are used duringfabrication to enable the proper placement of the source/drain regions80 and the source/drain extension regions 90. Usually the source/drainextension regions 90 are formed using the gate stack 100, 110 andextension sidewalls 140 as a mask. Furthermore, the source/drain regions80 are usually formed with the gate stack 100, 110 and source/drainsidewalls 150 as a mask.

Immediately above and surrounding the transistors is a layer ofdielectric insulation 160. The composition of dielectric insulation 160may be any suitable material such as SiO₂ or organosilicate glass(“OSG”). The dielectric material 160 electrically insulates the metalcontacts 170 that electrically connect the CMOS transistors shown inFIG. 1 to other active or passive devices (not shown) located throughoutthe semiconductor substrate 20. An optional dielectric liner (not shown)may be formed before the placement of the dielectric insulation layer160. If used, the dielectric liner may be any suitable material such assilicon nitride.

In the example application, the contacts 170 are comprised of W;however, any suitable material (such as Cu, Ti, or Al) may be used. Inaddition, an optional liner material 180 such as Ti, TiN, or Ta (or anycombination or layer stack thereof) may be used to reduce the contactresistance at the interface between the liner 180 and the silicidedregions 190 of the gate electrode 110 and source/drain regions 80.

Subsequent fabrication will create the “back-end” portion of theintegrated circuit. The back-end generally contains one or moreinterconnect layers (and possibly via layers) that properly routeelectrical signals and power though out the completed integratedcircuit.

The purpose of the silicide layer 190 formed within top portion of thegate electrode 110 and the source/drain regions 80 is the reduction ofthe contact resistance between the transistor and the electricalcontacts 170, 180. In accordance with the invention, the silicide 190 isNiSi. However, it is within the scope of the invention to use adifferent silicide, such as CoSi₂.

The NiSi silicide 190 formed within the gate electrode 110 in accordancewith the invention is more resistant to thermal induced agglomerationthroughout subsequent fabrication processes than standard silicides.This result is achieved by modifying the surface structure of the gateelectrode 110 with an ion implantation step that is performed early inthe fabrication process; as discussed more fully below.

Referring again to the drawings, FIGS. 2A-2G are cross-sectional viewsof a partially fabricated semiconductor wafer illustrating a process forforming an example PMOS transistor 120 in accordance with one embodimentof the present invention. Those skilled in the art of semiconductorfabrication will easily understand how to modify this process tomanufacture other types of transistors (such as a NMOS transistor) inaccordance with this invention.

FIG. 2A is a cross-sectional view of a transistor structure 120 afterthe formation of the shallow trench isolation structures 50 (not shown)and the gate layers 105, 115 on the top surface of a semiconductorsubstrate 20.

In the example application, the semiconductor substrate 20 is silicon;however any suitable material such as germanium or gallium arsenide maybe used. The example PMOS transistor 120 is formed within a n-wellregion 40 of the semiconductor substrate 20.

The first layer formed over the surface of the semiconductor substrate20 is a gate dielectric layer 105. As an example, the gate dielectriclayer 105 is silicon dioxide formed with a thermal oxidation process.However, the gate dielectric layer 105 may be any suitable material,such as nitrided silicon oxide, silicon nitride, or a high-k gatedielectric material, and may be formed using any one of a variety ofprocesses such as an oxidation process or thermal nitridation.

A gate electrode layer 115 is then formed on the surface of the gateoxide layer 105. The gate electrode layer 115 is comprised ofpolycrystalline silicon in the example application. However, it iswithin the scope of the invention to use other materials such as anamorphous silicon, a silicon alloy, or other suitable materials. Thegate electrode 115 may be formed using any process technique such aschemical vapor deposition (“CVD”) or physical vapor deposition (“PVD”).

In accordance with the best mode of the invention, an ion implant isperformed after the formation of the gate electrode layer 115. This ionimplant will influence the structure of the silicide 190 that is formedlater in the fabrication process (and described more fully below). Thebest mode ion implant is an Ar⁺ion implant, which modifies the surfacestructure of the gate electrode layer 115. Any suitable machine may beused to perform the ion implant such as the xRLeapII or the xRLeapQ(made by Applied Materials), the GSD Ultra or the GSD HC E² (made byAxcelis Technologies), or the VIISTA80 (made by Varian SemiconductorEquipment).

In the best mode application, an Ar⁺ion implant is performed using theAxcelis Technologies GSD Ultra ion implanter. The implant angle is0-10°; however, 0° is preferred. In addition, the implant energy mayrange from 5-35 keV; however, approximately 10 keV is preferred.Furthermore, the implant dose may range from 1×10E¹⁵-5×10E¹⁵; however,approximately 2×10E¹⁵ is preferred. Moreover, the beam current may rangefrom 3-12 mA; however, approximately 8 mA is preferred. It is to benoted that this ion implant may be followed by a standard post ionimplant clean. As shown in FIG. 2B, the ion implant will create an ionimplant region 195 within the top portion of the gate electrode layer115. At this stage of fabrication process the ion implant region 195 isamorphous.

It is within the scope of the invention to use other gases for the ionimplant. Ar⁺is used for the ion implant gas in the best mode applicationbecause it affects the physical structure of the surface of the gateelectrode layer 115. Another gas that would also affect the physicalstructure of the surface of gate electrode layer 115 is Sb⁺. Example ofother gases that could be used for the ion implant are N₂ ⁺and F⁺. Ifused, N₂ ⁺and F⁺would affect the chemical structure (rather than thephysical structure) of the surface region of the gate electrode layer115.

After a pattern and etch process, a gate stack having a gate dielectric100 and a gate electrode 110 will be formed from the gate dielectriclayer 105 and the gate electrode layer 115 (including the ion implantarea 195). This gate stack, shown in FIG. 2C, may be created through avariety of processes. For example, the gate stack may be created byforming a layer of photoresist over the semiconductor wafer, patterningthe photoresist, and then using the photoresist pattern to etch both thegate oxide layer 105 and the gate electrode layer 115. The gate stackmay be etched using an suitable etch process, such as an anisotropicetch.

The fabrication of the PMOS transistor 120 now continues with standardprocess steps. Generally, the next step in the fabrication of the PMOStransistor 120 is the formation of the extension regions 90.

As shown in FIG. 2D, extension sidewalls 140 are formed on the outersurface of the gate stack. The extension sidewalls 140 may be comprisedof an oxide, oxi-nitride, silicon dioxide, nitride, or any otherdielectric material or layers of dielectric materials. Furthermore, theextension sidewalls 140 may be formed with any suitable process, such asthermal oxidation, deposited oxide, CVD, or PVD.

These extension sidewalls 140 are now used as a template to facilitatethe proper placement of the extension regions 90. However, it is withinthe scope of the invention to form the extension regions 90 at any pointin the manufacturing process.

The extension regions 90 are formed near the top surface of thesemiconductor substrate 40 using any standard process. For example, theextension regions 90 may be formed by low-energy ion implantation, a gasphase diffusion, or a solid phase diffusion. The dopants used to createthe extension regions 90 for a PMOS transistor 120 are p-type (i.e.boron). However, other dopants or combinations of dopants may be used.

In the example application shown in FIG. 2D, the extension sidewalls 140are used to direct the dopant implantation to the proper location 90within the semiconductor substrate 40. Thus, the source and drainextension regions 90 initiate from points in the semiconductor substrate40 that are approximately at the outer corner of the extension sidewalls140.

At some point after the implantation of the extension regions 90, theextension regions 90 are activated by an anneal process (performed nowor later). This anneal step may be performed with any suitable processsuch as rapid thermal anneal (“RTA”). The annealing process will likelycause a lateral migration of each extension region toward the opposingextension region (as shown in FIG. 1).

Referring to FIG. 2E, source/drain sidewalls 150 are now formedproximate to the extension sidewalls 140. The source/drain sidewalls 150may be formed using any standard process. For example, the source/drainsidewalls 150 may be comprised of an oxide and/or a nitride that isformed with a CVD process and subsequently anisotropically etched. Nowthe source/drain sidewalls 150 are used as a template for thesource/drain implantation step. However, it is within the scope of theinvention to form the source/drain regions 80 at another point in themanufacturing process.

The source/drain regions 180 may be formed through any one of a varietyof processes, such as deep ion implantation or deep diffusion. Thedopants used to create the source/drain regions 80 for a PMOS transistorare typically boron; however, other dopants or combinations for dopantsmay be used.

The implantation of the dopants is self-aligned with respect to theouter edges of the source/drain sidewalls 150. However, it is to benoted that due to lateral straggling of the implanted species, thesource/drain regions 80—as well as the extension regions 90—initiateslightly inside the outer corner of the sidewalls 140,150 respectively.

In the example application, the source/drain regions 80 are activated bya second anneal step. (However, the extension region anneal and thesource/drain region anneal may be combined and performed at this pointin the fabrication process.) This anneal step acts to repair the damageto the semiconductor wafer and to activate the dopants. The activationanneal may be performed by any technique such as RTA, flash lampannealing (“FLA”), or laser annealing. This anneal step often causeslateral and vertical migration of dopants in the extension regions 90and the source/drain regions 80.

In addition, this anneal step will cause the recrystallization of theion implant region 195 (or the full crystallization of the ion implantregion 195 if this is the first anneal). The surface of therecrystallized ion implant region 195 is much smoother than the surfaceof a gate electrode 110 that has not been subject to the ion implantprocess in accordance with the invention. The result is an improvedthermal stability of the silicide 190 formed within the top portion ofthe gate electrode 110 later in the fabrication process.

As shown in FIG. 2F, the interface layer 200 is now formed over the topsurface of the semiconductor wafer. The interface layer is preferablycomprised of Ni; however, other suitable materials such as Co may beused.

An optional capping layer 210 may also be formed over the interfacelayer 200. If used, the capping layer 210 acts as a passivation layerthat prevents the diffusion of oxygen from ambient into the interfacelayer 200. The capping layer may be any suitable material, such as TiN.

In accordance with the invention, the semiconductor wafer is nowannealed with any suitable process, such as RTA. This anneal processwill cause a silicide 190 (i.e. a Ni-rich silicide or Ni mono-silicide)to form at the surface of the source/drain regions 80 and at the surfaceof the gate electrode 110 that was previously modified by the Ar⁺ionimplantation. These silicide regions 190 are shown in FIG. 2G. It is tobe noted that the interface layer 200 will only react with the activesubstrate (i.e. exposed Si); namely, the gate electrode 110 and thesource/drain 80. Therefore, the silicide 190 formed by the annealingprocess is considered a self-aligned silicide (“salicide”). It is alsoto be noted that the surface of source/drain regions 80 was not modifiedby the Ar⁺ion implant because the source/drain regions 80 were protectedduring the earlier ion implant step by the polysilicon of the gateelectrode layer 115.

The fabrication of the semiconductor wafer now continues, using standardprocess steps, until the semiconductor device is complete (see FIG. 1).Generally, the next step is the removal of the unwanted portions of theinterface layer 200 (and capping layer 210) through a wet etch process(i.e. using a mixture of sulfuric acid, hydrogen peroxide, and water).

It is within the scope of the invention to perform a second anneal (suchas a RTA) at this point in the manufacturing process in order to furtherreact the suicide 190 with the gate electrode 110 and the source/drainregions 80. If the initial anneal process did not complete thesilicidation process, this second anneal will ensure the formation of amono-silicide NiSi which lowers the sheet resistance of the silicide190.

Next, the dielectric insulator layer 160 may be formed usingplasma-enhanced chemical vapor deposition (“PECVD”) or another suitableprocess. The dielectric insulator 160 may be comprised of any suitablematerial such as SiO₂ or OSG.

The contacts 170 are formed by etching the dielectric insulator layer160 to expose the desired gate, source and/or drain. An example etchprocess is anisotropic etch. The etched spaces are usually filled with aliner 180 to improve the electrical interface between the silicide 190and the contact 170. Then contacts 170 are formed within the liner 180;creating the electrical interconnections between various semiconductorcomponents located within the semiconductor substrate 20.

As discussed above, the fabrication of the final integrated circuitcontinues with the fabrication of the back-end structure. Once thefabrication process is complete, the integrated circuit will be testedand then packaged.

The ion implantation of the gate electrode 110 before the formation ofthe gate stack in accordance with the invention will help to preventthermal induced agglomeration of the silicide 190 during subsequentfabrication processes. As shown in FIG. 3, the NiSi layer 190 formedwithin the gate electrode 110 after an ion implant process is morestable at higher process temperatures (as measured by the sheetresistance) than a NiSi layer formed without the inventive process.Therefore, the silicide 190 formed in accordance with this inventionwill have an improved thermal stability and will therefore withstandhigher manufacturing process temperatures (i.e. over 500° C.) duringsubsequent processing steps.

One of the variations to the present invention is to perform the ionimplant after the source/drain implant but before the anneal of thesource/drain regions. Using this alternative fabrication process,standard manufacturing steps would be used to build the transistor 120to the point of the implant of the source/drain regions 80. An Ar⁺ionimplant would then be performed (using the ion implant machines andprocess parameters listed above) subsequent to the dopant implant of thesource/drain regions 80 but prior to the source/drain anneal. This ionimplant would modify the top surface of the gate electrode 110 asdescribed above, creating a ion implant area 195. Next, a source/drainanneal (preferably using a RTA process) would be performed and then theinterface layer 200 would be formed over the surface of thesemiconductor wafer. After a suitable annealing process, such as RTA, asilicide 190 would be formed on the top surface of the gate electrode110. The fabrication process would then continue with standard processsteps. However, the silicide 190 formed with this alternative processflow will help to prevent thermal induced agglomeration of the silicide190 during subsequent fabrication processes.

Various additional modifications to the invention as described above arewithin the scope of the claimed invention. As an example, interfaciallayers may be formed between any of the layers shown. Similarly, any ofthe sidewall layers described in the example application may be omitted.For example, the extension sidewalls 140 may be omitted withoutdeparting from the scope of the invention. Moreover, if extensionsidewalls 140 are omitted than the thickness of source/drain sidewalls150 may be increased.

It is to be noted that an anneal process may be performed after any stepin the above-described fabrication process. For instance, an annealingstep may be performed after the implantation of the source/drainextension regions 90 but before the formation of the source/drainsidewalls 150. When used, the anneal process can improve themicrostructure of materials and thereby improve the quality of thesemiconductor structure.

This invention may be implemented in a sidewall spacer structure that iscomprised of different materials or layers than is described above. Inaddition, this invention may be implemented in other semiconductorstructures such as capacitors or diodes, and also in differenttransistor structures such as biCMOS and bipolar transistors.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only, and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the invention. Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the invention shouldbe defined in accordance with the following claims and theirequivalents.

1. A method for making a transistor, comprising: providing asemiconductor substrate; forming a gate dielectric layer over saidsemiconductor substrate; forming a gate electrode layer over said gatedielectric layer; and performing an ion implant on said gate electrodelayer.
 2. The method of claim 1 further comprising: etching said gateelectrode layer and said gate dielectric layer to form a gate stackhaving a gate electrode and a gate dielectric; forming extensionsidewalls coupled to said gate stack; implanting extension regionswithin a top surface of said semiconductor substrate; formingsource/drain sidewalls coupled to said extension sidewalls; implantingsource/drain regions within a top surface of said semiconductorsubstrate; annealing said semiconductor substrate; forming an interfacelayer over said semiconductor substrate; and performing an anneal tocreate a silicide within a top surface of said gate electrode.
 3. Themethod of claim 1 wherein said ion implant is a Ar⁺ion implant.
 4. Themethod of claim 1 wherein said ion implant is a N₂ ⁺ion implant.
 5. Themethod of claim 1 wherein said ion implant is a F⁺ion implant.
 6. Themethod of claim 1 wherein said ion implant is a Sb⁺ion implant.
 7. Themethod of claim 1 wherein said gate electrode layer comprisespolycrystalline silicon.
 8. The method of claim 1 wherein said gateelectrode layer comprises amorphous silicon.
 9. The method of claim 1wherein said transistor is a CMOS transistor.
 10. The method of claim 1wherein said transistor is a PMOS transistor.
 11. The method of claim 1wherein said transistor is a NMOS transistor.
 12. The method of claim 2wherein said anneal to create a silicide is a rapid thermal anneal. 13.The method of claim 2 wherein said interface layer comprises Ni.
 14. Themethod of claim 2 wherein said interface layer comprises Co.
 15. Themethod of claim 2 wherein said silicide is a self-aligned silicide. 16.A method for forming a silicide on a gate of a transistor, comprising:providing a semiconductor substrate; forming a gate dielectric layerover said semiconductor substrate; forming a gate electrode layer oversaid gate dielectric layer, said gate electrode layer comprisingpolycrystalline silicon; performing an Ar⁺ion implant on said gateelectrode layer; etching said gate electrode layer and said gatedielectric layer to form a gate stack having a gate electrode and a gatedielectric; forming extension sidewalls coupled to said gate stack;implanting extension regions within a top surface of said semiconductorsubstrate; forming source/drain sidewalls coupled to said extensionsidewalls; implanting source/drain regions within a top surface of saidsemiconductor substrate; annealing said semiconductor substrate torecrystallize a surface region of said gate electrode modified by saidAr⁺ion implant; forming an interface layer over said semiconductorsubstrate, said interface layer including Ni; and performing a rapidthermal anneal to create a nickel silicide within said surface region ofsaid gate electrode.
 17. The method of claim 16 further including thestep of forming a cap layer over said interface layer prior to said stepof performing a rapid thermal anneal.
 18. The method of claim 16 furthercomprising: performing a second rapid thermal anneal subsequent to saidstep of performing a rapid thermal anneal.
 19. A method for forming asilicide on a gate of a transistor, comprising: providing asemiconductor substrate; forming a gate dielectric layer over saidsemiconductor substrate; forming a gate electrode layer over said gatedielectric layer; etching said gate electrode layer and said gatedielectric layer to form a gate stack having a gate electrode and a gatedielectric; forming extension sidewalls coupled to said gate stack;implanting extension regions within a top surface of said semiconductorsubstrate; forming source/drain sidewalls coupled to said extensionsidewalls; implanting source/drain regions within a top surface of saidsemiconductor substrate; performing an Ar⁺ion implant; annealing saidsemiconductor substrate; forming an interface layer over saidsemiconductor substrate; and performing an anneal to create a silicideon a top surface of said gate electrode.
 20. The method of claim 19wherein said gate electrode layer comprises polycrystalline silicon. 21.The method of claim 19 wherein said gate electrode layer comprisesamorphous silicon.
 22. The method of claim 19 wherein said transistor isa CMOS transistor.
 23. The method of claim 19 wherein said transistor isa PMOS transistor.
 24. The method of claim 19 wherein said transistor isa NMOS transistor.
 25. The method of claim 19 wherein said anneal tocreate a silicide is a rapid thermal anneal.
 26. The method of claim 19wherein said interface layer comprises Ni.
 27. The method of claim 19wherein said interface layer comprises Co.
 28. The method of claim 19wherein said silicide is a self-aligned silicide.